I design logic that ends up as silicon_
I'm Colin Yap, a Year 2 MEng Electrical & Electronic Engineering student in Malaysia, heading toward RTL design and verification — the work of describing a chip in code and proving it behaves. I also build robots, embedded systems and circuit boards.
About. Who I am, and how I ended up pointed at chip design.
I'm a Year 2 MEng (Hons) student at the University of Nottingham Malaysia, and I've spent it building across as much of engineering as I can reach — mechanical assemblies, embedded firmware, control systems, computer vision, and digital logic. The common thread isn't a single field; it's that I like taking something from a rough idea to a thing that actually works.
That's meant a PID-controlled line-following robot with computer vision, a wireless robotic hand driven by a flex-sensor glove, and a business card etched onto a circuit board. Each one pulled me deeper into a different discipline — motor control, wireless comms, mechanical design, board layout.
Digital design is where that's settled. I've built a RISC-V processor in Verilog, added two instruction set extensions to it, and pushed it all the way through to a manufacturable chip layout using the open-source OpenLane flow. My aim is RTL design and design verification in Malaysia's semiconductor industry.
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Colin Yap Ren Feng · Selangor, Malaysia · 2026 · github · linkedin